1. Field of Invention
The present invention generally relates to testing technology for a tester, and more particularly to a device and method for testing multiple input-output ports.
2. Description of Related Art
Conventional testers can only test a fixed number of input-output (IO) ports, for example, 32 or 64 I/O ports at one time, limiting the testing capacity for a large-size memory. As shown in FIG. 1, which shows a conventional method for testing I/O ports, in which corresponding relationship between the I/O ports of a device under test and probes is one-to-one. Also, probe card 10 is directly connected to device under test (DUT) card 20 via I/O ports IO0, IO1, . . . , IO31.
When the number of I/O ports of a device under testing is larger than 32, for example, 64, two tests are required for the tester to complete an I/O testing. It therefore causes time delay in the manufacturing process of electronic devices, if the number of I/O ports under testing is larger than the capacity that the tester can provide.